1. Field of the Invention
Embodiments of the present invention generally relate to a method of depositing a gate dielectric layer of a thin film transistor (TFT).
2. Description of the Related Art
Active matrix liquid crystal displays (AMLCD) have eliminated many problems associated with passive displays. For example, the fabrication of active matrix liquid crystal displays has enabled display screens to achieve greater brightness, enhanced readability, a greater variety of color shades, and broader viewing angles compared to displays that employ other technologies. Active matrix liquid crystal displays generally comprise an array of picture elements called pixels. An electronic switch is associated with each pixel in the display to control the operation thereof. Various electronic switches, such as thin film transistors (TFTs) and organic light emitting diodes (OLEDs), have been investigated to control pixel operation. Thin film transistors, in particular, offer a high degree of design flexibility and device performance.
Thin film transistors generally are formed on large area substrates having a high degree of optical transparency, such as glass substrates. FIG. 1 depicts a cross-sectional schematic view of a thin film transistor 122 having a bottom gate structure. The thin film transistor 122 includes a glass substrate 101 having an underlayer 102 formed on the surface thereof. A gate is formed on the underlayer 102. The gate comprises a gate metal layer 104 and a gate dielectric 108. The gate controls the movement of charge carriers in the transistor. The gate dielectric 108 formed over the gate metal layer 104 electrically isolates the gate metal layer 104 from semiconductor layers 110, 114a, 114b, formed thereon, each of which may function to provide charge carriers to the transistor. An etch stop layer 112 is formed on the semiconductor layer 110. A source region 118a of the transistor is formed on semiconductor layer 114a, and a drain region 118b of the transistor is formed on semiconductor layer 114b. A passivation layer 120 encapsulates the TFT 122 to protect it from environmental hazards such as moisture and oxygen. A conductive layer 116 is formed in the passivation layer 120.
FIG. 1 shows only one of the many types of TFTs. Other TFT structures having similar types of layers in different arrangements can be formed by using different deposition and patterning sequences.
For TFTs of any structure, each layer is critical with respect to the electrical performance of the TFT. In particular, the gate dielectric layer must have certain qualities, e.g., low flatband voltage (Vfb) and high breakdown voltage (VB), in order for the transistor to have overall desirable electrical characteristics, such as low charge density (Dit), low threshold voltage (Vth), and low leakage current, among others.
It is particularly desirable that low temperature polysilicon (LTPS) TFTs have a low flatband voltage. LTPS TFTs generally provide displays having a higher resolution than displays containing amorphous silicon TFTs due to the greater mobility of electrons through LTPS TFTs than through amorphous silicon TFTs. The greater mobility of electrons through LTPS TFTs also increases the importance of achieving a low flatband voltage.
While methods have been developed to deposit gate dielectric layers for TFTs, there remains a need for a method of depositing gate dielectric layers with improved electrical characteristics.